Many systems, such as delay-locked loops (DLL's), perform a phase shift of an input signal to produce a phase-shifted output signal. Such systems typically employ adjustable delay elements to provide the desired phase shift. A common example of an adjustable delay element is a current-starved inverter circuit in which the effective propagation delay of the inverter is varied by controlling, via a control voltage, the amount of current available to charge and discharge a load capacitance. Unfortunately, such prior art phase shifters typically have finite adjustment ranges. The limits of the adjustment ranges for prior art phase shifters are typically a result of the manner in which the phase shift is achieved.
Given a periodic first signal (the input signal) and a periodic second signal (the output signal) that is a delayed version of the first signal, the input and output signals are said to be "out of phase." Typical prior art phase shifters rely on the relationship between the phase difference (.phi.) and the time delay (.DELTA.t) between the input signal and the output signal, which is expressed by the following equation: EQU .phi.=2.pi.f.DELTA.t (1)
The input and the output signals can be expressed by the following equations: EQU V.sub.in =V.sub.MAX sin (2.pi.ft); (2) EQU V.sub.out =V.sub.MAX sin (2.pi.ft+.phi.); (3)
wherein VMAX is the maximum amplitude of the signal, f is the frequency and t is time. Substituting equation (1) into equation (3) yields: EQU V.sub.out =A sin 2.pi.f(t+.DELTA.t) (4)
When the frequency of the input signal is known, it is a simple matter to design a delay circuit to provide the maximum desired At. The range of time delay, and therefore phase shift, is varied by adjusting the amount of current available to charge and discharge the load capacitance. The lower endpoint of the phase adjustment range is fixed by the inherent propagation delay of the delay circuit, and the upper endpoint of the phase adjustment range is fixed by the minimum current, the load capacitance and noise considerations.
When typical prior art delay elements are used in a DLL, acquisition of lock must be carefully managed. If the frequency of the input signal is variable, there may be more than one value of the control voltage that allows lock. Further, if the loop should happen to lock with the control voltage near the limit of the delay element's range, it is possible for small disturbances or drifts in the control voltage to cause the loop to lose lock. To prevent such problems, tight restrictions are typically placed on the input frequency range. Further, the control voltage must typically be initialized near the center of the control voltage range.